1. Field of the Invention
The present invention relates to an apparatus and method for controlling timing of transfer requests within a data processing apparatus.
2. Description of the Prior Art
A data processing apparatus will typically have a number of logic units that are interconnected via a bus, with data being transferable between the logic units via the bus. To effect such a transfer, a first logic unit may output a transfer request on to the bus, this transfer request being destined for a second logic unit. The second logic unit will then retrieve the transfer request from the bus and perform an appropriate operation in order to process the transfer request. Logic units that are designed to initiate transfer requests can be referred to as xe2x80x9cmasterxe2x80x9d logic units, whilst logic units that are designed to be recipients of such transfer requests can be referred to as xe2x80x9cslavexe2x80x9d logic units.
The master logic unit initiating a transfer request must drive a number of transfer request signals on to the bus in order to sufficiently define the transfer request to enable the slave logic unit to perform the appropriate operation in response to the transfer request. Hence, the master logic unit will typically output various control signals, for example identifying the type of operation to be performed by the slave logic unit, (e.g. a read or a write operation), the type of transfer (e.g, with regards to addresses, whether the transfer is a sequential, or non-sequential transfer), the size of the access (e.g. word, byte), the operating mode of the master logic units (e.g. supervisor or user mode), etc. Further, the master logic unit will typically output an address signal identifying the address at which the slave logic unit is to apply the operation.
It will be apparent that the master logic unit will require a certain amount of time to drive the necessary transfer request signals to a valid value on the bus, and that to ensure correct operation, the slave logic unit should not retrieve the signals from the bus, or at least not perform any operation required by the transfer request, until all of the necessary transfer request signals have been driven on the bus to the correct value by the master logic unit.
Generally a system clock is employed to control the frequency of operation of the various logic units within the data processing apparatus, and the slave logic unit will be arranged to sample the contents of the bus at a particular point in a clock cycle, for example the falling edge of the clock cycle. If all of the master logic units are able to drive the necessary transfer request signals on to the bus during the same clock cycle that they initiate a transfer request, then clearly the slave logic unit can sample the contents of the bus at the end of that clock cycle, and proceed to perform the necessary operation. However, if one or more of the master logic units is not able to output all of the necessary transfer request signals on to the bus during the same clock cycle that it initiates a transfer request, then it is important that the slave logic unit does not perform any operation on the basis of the contents of the bus at the end of that cycle, but rather waits until a subsequent clock cycle before reading the contents of the bus and performing the necessary operation.
Hence, prior art data processing apparatus have typically fallen into two categories. If all of the master logic units within the data processing apparatus are capable of issuing the necessary transfer request signals on to the bus during the same clock cycle that they initiate a transfer request, then the second logic unit is merely arranged to read the contents of the bus at the earliest opportunity, and perform the necessary operation. However, for data processing apparatus where at least one of the master logic units is not able for at least certain types of transfers to reliably provide the necessary transfer request signals on the bus at the end of the clock cycle in which the transfer request is initiated, then for those types of transfer requests a delay is typically inserted into the process, such that the slave logic unit does not read the contents of the bus until the end of the delay.
It will be appreciated that the insertion of a delay for certain types of bus transfers adversely affects the performance of the data processing apparatus. This is particularly true where the processing request happens to be being issued by a master logic unit that can provide the necessary signals on the bus during the same clock cycle that the transfer request is initiated, since the delay is applied irrespective of the master logic unit issuing the transfer request. In effect, the performance of all of the master logic units is restricted by the performance of the slowest master logic unit in the data processing apparatus.
Further, the above approach can unnecessarily affect the performance of even the slowest logic unit in the data processing apparatus in cases where its signal timing improves. One example of this is when the system is run at a lower clock frequency than originally designed, and, as a result of this, the original timing constraints disappear.
It is hence an object of the present invention to provide an improved technique for controlling timing of transfer requests within a data processing apparatus.
Viewed from a first aspect, the present invention provides a data processing apparatus, comprising: a bus for interconnecting a number of logic units, data being transferable between the logic units via the bus; a first logic unit for issuing onto a bus a transfer request and a type signal indicating the type of the transfer request; a second logic unit for receiving the transfer request from the bus and performing an operation in response to the transfer request; the first logic unit being arranged to encode within the type signal a timing indication used to control the timing of the receipt of the transfer request by the second logic unit.
In accordance with the present invention, when the first logic unit issues on to the bus a transfer request, and a type signal indicating the type of the transfer request, it is also arranged to encode within the type signal a timing indication used to control the timing of the receipt of the transfer request by the second logic unit. Hence, if the first logic unit is able to issue the necessary transfer request signals on to the bus relatively quickly, for example as compared with other logic units within the data processing apparatus, then this can be reflected within the timing indication encoded within the type signal, and can be used to avoid any unnecessary delay in the receipt of the transfer request by the second logic unit. Similarly, if the first logic unit cannot issue the necessary transfer request signals quite so quickly, this can also be reflected within the timing indication encoded within the type signal, and can be used to ensure that an appropriate delay occurs before the transfer request is received from the bus by the second logic unit.
By this approach, the performance of the data processing apparatus can be increased, since the performance of transfer requests is no longer restricted by the performance of the slowest logic unit that may initiate a transfer request. Instead, the timing of the transfer request can be governed by the actual performance of the logic unit issuing the transfer request, and therefore the data processing apparatus can take advantage of the performance increase available when logic units drive the necessary transfer request signals on to the bus relatively quickly, and hence the standard delay typically inserted by prior art data processing apparatus is not required.
Further, in accordance with the present invention, the performance loss that occurs in prior art systems when signal timing improves under specific circumstances can also be avoided. For example, if the system is run at a lower clock frequency than originally designed, for example as may occur during testing, then a particular logic unit that might normally require a delay to be inserted when it issues a transfer request may no longer need that delay to be inserted because of the reduced clock frequency, and this can be reflected in the timing indication encoded within the type signal issued by that logic unit.
The second logic unit may be arranged to receive the type signal directly, and to determine from the timing indication when to receive the transfer request from the bus. However, in preferred embodiments, the data processing apparatus further comprises a decoder for asserting a select signal to the second logic unit to cause the second logic unit to read the transfer request from the bus, the decoder being arranged to receive the type signal from the bus and to determine from the timing indication when to assert the select signal to the second logic unit.
Hence, in preferred embodiments, the decoder determines from the transfer request signals issued by the first logic unit which logic unit should receive the transfer request, and from the timing indication encoded within the type signal determines when to inform that logic unit that it should read the transfer request from the bus.
In preferred embodiments, the data processing apparatus further comprises a clock generator for generating a clock signal having a predetermined clock cycle, the timing indication encoded in the type signal indicating in which clock cycle the transfer request should be received from the bus by the second logic unit.
Preferably, the timing indication identifies whether the transfer request is available to be received from the bus by the second logic unit during the same clock cycle that the type signal is generated by the first logic unit, or in a predetermined subsequent clock cycle.
It will be appreciated by those skilled in the art that there are various types of transfer request which may be issued by the first logic unit, and that the timing constraints may be different for different types of transfer request. Certain types of transfer request can inherently be performed quicker than others. For example, burst transfers to sequential addresses, commonly known as sequential transfers, are typically relatively fast, because the signals output on to the bus are generally related to the signals of the previous transfer and hence little change to the signals is often required. In contrast, certain types of transfer request, such as non-sequential transfers, in which the address of the transfer is unrelated to the address of the previous transfer, are often relatively slow, since the various transfer request signals to be issued on to the bus are generally unrelated to those of the previous transfer.
In preferred embodiments, if the transfer request is a non-sequential transfer and the first logic unit is able to drive on to the bus during the same clock cycle that the type signal is generated the transfer request signals required by the second logic unit, the timing indication encoded into the type signal indicates that the transfer request is available to be received from the bus by the second logic unit during the same clock cycle that the type signal is generated by the first logic unit. However, if the transfer request is a non-sequential transfer and the first logic unit is able to drive on to the bus by the predetermined subsequent clock cycle the transfer request signals required by the second logic unit, then in preferred embodiments the timing indication encoded into the type signal indicates that the transfer request is available to be received from the bus by the second logic unit during the predetermined subsequent clock cycle.
In preferred embodiments, the data processing apparatus further comprises: a decoder for asserting a select signal to the second logic unit to cause the second logic unit to read the transfer request from the bus, the decoder being arranged to receive the type signal from the bus; if the timing indication indicates that the transfer request is available to be received from the bus by the second logic unit during the same clock cycle that the type signal is generated by the first logic unit, then the decoder being arranged to assert the select signal without delay; and if the timing indication indicates that the transfer request is available to be received from the bus by the second logic unit during the predetermined subsequent clock cycle, then the decoder being arranged to delay asserting the select signal until said predetermined subsequent clock cycle.
The predetermined subsequent clock cycle can be chosen to be any subsequent clock cycle, and will depend on factors such as the operating speed of the logic unit issuing the transfer request. However, in preferred embodiments the predetermined subsequent clock cycle is the clock cycle immediately following the clock cycle in which the type signal is generated by the first logic unit.
Typically, the second logic unit is arranged to read the transfer request from the bus at a predetermined point in the clock cycle indicated by the timing indication. Hence, for example, the second logic unit may be arranged to sample the contents of the bus during the falling edge of the clock, and hence will read the transfer request from the bus during the falling edge of the clock in the clock cycle indicated by the timing indication.
It will be appreciated by those skilled in the art that the format of the type signal can be varied as required, without departing from the scope of the present invention. However, in preferred embodiments the type signal is a two-bit signal, and the value of the two bits provides the timing indication in addition to identifying the type of the transfer request.
Viewed from a second aspect the present invention provides a method of controlling timing of transfer requests employed in a data processing apparatus to transfer data between logic units interconnected by a bus, comprising the steps of: issuing onto the bus from a first logic unit a transfer request and a type signal indicating the type of the transfer request; receiving at a second logic unit the transfer request from the bus and performing an operation in response to the transfer request; and encoding within the type signal a timing indication used to control the timing of the receipt of the transfer request by the second logic unit.